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Proceedings Paper

HVM die yield improvement as a function of DRSEM ADC
Author(s): Sonu Maheshwary; Terry Haas; Steve McGarvey
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Paper Abstract

Given the current manufacturing technology roadmap and the competitiveness of the global semiconductor manufacturing environment in conjunction with the semiconductor manufacturing market dynamics, the market place continues to demand a reduced die manufacturing cost. This continuous pressure on lowering die cost in turn drives an aggressive yield learning curve, a key component of which is defect reduction of manufacturing induced anomalies. In order to meet and even exceed line and die yield targets there is a need to revamp defect classification strategies and place a greater emphasize on increasing the accuracy and purity of the Defect Review Scanning Electron Microscope (DRSEM) Automated Defect Classification (ADC) results while placing less emphasis on the ADC results of patterned/un-patterned wafer inspection systems. The increased emphasis on DRSEM ADC results allows for a high degree of automation and consistency in the classification data and eliminates variance induced by the manufacturing staff. This paper examines the use of SEM based Auto Defect Classification in a high volume manufacturing environment as a key driver in the reduction of defect limited yields.

Paper Details

Date Published: 16 April 2010
PDF: 9 pages
Proc. SPIE 7638, Metrology, Inspection, and Process Control for Microlithography XXIV, 763822 (16 April 2010); doi: 10.1117/12.846700
Show Author Affiliations
Sonu Maheshwary, Microchip (United States)
Terry Haas, Microchip (United States)
Steve McGarvey, Hitachi High Technologies America (United States)


Published in SPIE Proceedings Vol. 7638:
Metrology, Inspection, and Process Control for Microlithography XXIV
Christopher J. Raymond, Editor(s)

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