Share Email Print
cover

Proceedings Paper

Measurements and sensitivities of LWR in poly spacers
Author(s): Guy Ayal; Eitan Shauly; Shimon Levi; Amit Siany; Ofer Adan; Yosi Shacham-Diamand
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

LER and LWR have long been considered a primary issue in process development and monitoring. Development of a low power process flavors emphasizes the effect of LER, LWR on different aspects of the device. Gate level performance, particularly leakage current at the front end of line, resistance and reliability in the back-end layers. Traditionally as can be seen in many publications, for the front end of line the focus is mainly on Poly and Active area layers. Poly spacers contribution to the gate leakage, for example, is rarely discussed. Following our research done on sources of gate leakage, we found leakage current (Ioff) in some processes to be highly sensitive to changes in the width of the Poly spacers - even more strongly to the actual Poly gate CDs. Therefore we decided to measure Poly spacers LWR, its correlation to the LWR in the poly, and its sensitivity to changes in layout and OPC. In our last year publication, we defined the terms LLER (Local Line Edge Roughness) and LLWR (Local Line Width Roughness). The local roughness is measured as the 3-sigma value of the line edge/width in a 5-nm segment around the measurement point. We will use these terms in this paper to evaluate the Poly roughness impact on Poly spacer's roughness. A dedicated test chip was designed for the experiments, having various transistors layout configurations with different densities to cover the all range of process design rules. Applied Materials LER and LWR innovative algorithms were used to measure and characterize the spacer roughness relative to the distance from the active edges and from other spaces. To accurately measure all structures in a reasonable time, the recipes were automatically generated from CAD. On silicon, after poly spacers generation, the transistors no longer resemble the Poly layer CAD layout, their morphology is different compared with Photo/Etch traditional structures , and dimensions vary significantly. In this paper we present metrology and characterization of poly spacer LLWR and LLER compared to that of the poly gate in various transistor shapes, showing that the relation between them depends on the transistor architecture (final layout, including OPC). We will show how the spacer deposition may reduce, keep or even enlarge the roughness measured on Poly, depending on transistor layout , but surprisingly, not dependent on proximity effects.

Paper Details

Date Published: 1 April 2010
PDF: 6 pages
Proc. SPIE 7638, Metrology, Inspection, and Process Control for Microlithography XXIV, 76380O (1 April 2010); doi: 10.1117/12.846601
Show Author Affiliations
Guy Ayal, Tower Semiconductor Ltd. (Israel)
Tel-Aviv Univ. (Israel)
Eitan Shauly, Tower Semiconductor Ltd. (Israel)
Technion-Israel Institute of Technology (Israel)
Shimon Levi, Applied Materials, Inc. (Israel)
Amit Siany, Applied Materials, Inc. (Israel)
Ofer Adan, Applied Materials, Inc. (Israel)
Yosi Shacham-Diamand, Tel-Aviv Univ. (Israel)


Published in SPIE Proceedings Vol. 7638:
Metrology, Inspection, and Process Control for Microlithography XXIV
Christopher J. Raymond, Editor(s)

© SPIE. Terms of Use
Back to Top