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Proceedings Paper

Electrical validation of through process OPC verification limits
Author(s): Omprakash Jaiswal; Rakesh Kuncha; Taksh Bharat; Vipin Madangarli; Edward Conrad; James Bruce; Sajan Marokkey
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Paper Abstract

Electrical validation of through process OPC verification limits in 32nm process technology is presented in this paper. Correlation plots comparing electrical and optical simulations are generated by weighting the probability of occurrence of each process conditions. The design of electrical layouts is extended to sub ground rules to force failure and derive better correlation between electrical and simulated outputs. Some of these sub ground rule designs amplify the failures induced by exposure tool, such as optical aberrations. Observations in this regard will be reported in the paper. Sensitivity with respect to dimensions, orientations and wafer distribution will be discussed in detail.

Paper Details

Date Published: 1 April 2010
PDF: 8 pages
Proc. SPIE 7638, Metrology, Inspection, and Process Control for Microlithography XXIV, 76380U (1 April 2010); doi: 10.1117/12.846572
Show Author Affiliations
Omprakash Jaiswal, IBM Corp. (India)
Rakesh Kuncha, IBM Corp. (India)
Taksh Bharat, IBM Corp. (India)
Vipin Madangarli, IBM Corp. (India)
Edward Conrad, IBM Corp. (United States)
James Bruce, IBM Corp. (United States)
Sajan Marokkey, Infineon Technologies AG (United States)


Published in SPIE Proceedings Vol. 7638:
Metrology, Inspection, and Process Control for Microlithography XXIV
Christopher J. Raymond, Editor(s)

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