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Proceedings Paper

Interlayer self-aligning process for 22nm logic
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Paper Abstract

Line/space dimensions for 22nm logic are expected to be ~35nm at ~70nm pitch for metal 1. However, the contacted gate pitch will be ~90nm because of contact-to-gate spacing limited by alignment. A process for self-aligning contact to gates and diffusions could reduce the gate pitch and hence directly reduce logic and memory cells sizes. Self-aligned processes have been in use for many years. DRAMs have had bit-line and storage-node contacts defined in the critical direction by the row-lines. More recently, intra-layer self-alignment has been introduced with spacer double patterning, in which pitch division is accomplished using sidewall spacers defined by a removable core.[1] This approach has been extended with pitch division by 4 to the 7nm node.[2] The introduction of logic design styles which use strictly one-directional lines for the critical levels gives the opportunity for extending self-alignment to inter-layer applications in logic and SRAMs. Although Gridded Design Rules have been demonstrated to give area-competitive layouts at existing 90, 65, and 45nm logic nodes while reducing CD variability[3], process extensions are required at advanced nodes like 22nm to take full advantage of the regular layouts. An inter-layer self-aligning process has been demonstrated with both simulations and short-loop wafers. An extension of the critical illumination step for active and gate contacts will be described.

Paper Details

Date Published: 3 March 2010
PDF: 7 pages
Proc. SPIE 7640, Optical Microlithography XXIII, 76401V (3 March 2010); doi: 10.1117/12.846562
Show Author Affiliations
Michael C. Smayling, Tela Innovations, Inc. (United States)
Stewart Robertson, KLA-Tencor (United States)
Damian Lacey, Cavendish Kinetics, Inc. (United States)
Sanjay Kapasi, KLA-Tencor (United States)


Published in SPIE Proceedings Vol. 7640:
Optical Microlithography XXIII
Mircea V. Dusa; Will Conley, Editor(s)

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