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Proceedings Paper

Towards nanoimprint lithography-aware layout design checking
Author(s): Hayden Taylor; Duane Boning
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Paper Abstract

Just as the simulation of photolithography has enabled resolution-enhancement through Optical Proximity Correction, the physical simulation of nanoimprint lithography is needed to guide the design of products that will use this process. We present an extremely fast method for simulating thermal nanoimprint lithography. The technique encapsulates the resist's mechanical behavior using an analytical function for its surface deformation when loaded at a single location. It takes a discretized stamp design and finds resist and stamp deflections in a series of steps. We further accelerate the simulation of feature-rich patterns by pre-computing dimensionless relationships between the applied pressure, the resist's mechanical properties, and the residual layer thickness, for stamps patterned with uniform arrays of a variety of common feature shapes. The approach is fast enough to be used iteratively when selecting processing parameters and refining layouts. The approach is demonstrated in action with three nanoimprint test-patterns, and describes experimentally measured residual layer thickness variations to within 10-15% or better. Finally, our technique is used to propose nanoimprint-aware design rules.

Paper Details

Date Published: 3 April 2010
PDF: 12 pages
Proc. SPIE 7641, Design for Manufacturability through Design-Process Integration IV, 76410U (3 April 2010); doi: 10.1117/12.846499
Show Author Affiliations
Hayden Taylor, Massachusetts Institute of Technology (United States)
Duane Boning, Massachusetts Institute of Technology (United States)


Published in SPIE Proceedings Vol. 7641:
Design for Manufacturability through Design-Process Integration IV
Michael L. Rieger; Joerg Thiele, Editor(s)

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