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Proceedings Paper

Applicability of extreme ultraviolet lithography to fabrication of half pitch 35nm interconnects
Author(s): Hajime Aoyama; Yuusuke Tanaka; Kazuo Tawarayama; Naofumi Nakamura; Eiichi Soda; Noriaki Oda; Yukiyasu Arisawa; Taiga Uno; Takashi Kamo; Kentaro Matsunaga; Daisuke Kawamura; Toshihiko Tanaka; Hiroyuki Tanaka; Shuichi Saito; Ichiro Mori
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Paper Abstract

Extreme ultraviolet lithography (EUVL) is moving into the phase of the evaluation of integration for device fabrication. This paper describes its applicability to the fabrication of back-end-of-line (BEOL) test chips with a feature size of hp 35 nm, which corresponds to the 19-nm logic node. The chips were used to evaluate two-level dual damascene interconnects made with low-k film and Cu. The key factors needed for successful fabrication are a durable multi-stack resist process, accurate critical dimension (CD) control, and usable overlay accuracy for the lithography process. A multi-stack resist process employing 70-nm-thick resist and 25-nm-thick SOG was used on the Metal-1 (M1) and Metal- 2 (M2) layers. The resist thickness for the Via-1 (V1) layer was 80 nm. To obtain an accurate CD, we employed rulebased corrections involving mask CD bias to compensate for flare variation, mask shadowing effects, and optical proximity effects. With these corrections, the CD variation for various 35-nm trench and via patterns was about ± 1 nm. The total overlay accuracy (|mean| ± 3σ) for V1 to M1 and M2 to V1 was below 12 nm. Electrical tests indicate that the uses of Ru barrier metal and scalable porous silica are keys to obtaining operational devices. The evaluation of a BEOL test chip revealed that EUVL is applicable to the fabrication of hp-35-nm interconnects and that device development can be accelerated.

Paper Details

Date Published: 22 March 2010
PDF: 12 pages
Proc. SPIE 7636, Extreme Ultraviolet (EUV) Lithography, 76361N (22 March 2010); doi: 10.1117/12.846325
Show Author Affiliations
Hajime Aoyama, Semiconductor Leading Edge Technologies, Inc. (Japan)
Yuusuke Tanaka, Semiconductor Leading Edge Technologies, Inc. (Japan)
Kazuo Tawarayama, Semiconductor Leading Edge Technologies, Inc. (Japan)
Naofumi Nakamura, Semiconductor Leading Edge Technologies, Inc. (Japan)
Eiichi Soda, Semiconductor Leading Edge Technologies, Inc. (Japan)
Noriaki Oda, Semiconductor Leading Edge Technologies, Inc. (Japan)
Yukiyasu Arisawa, Semiconductor Leading Edge Technologies, Inc. (Japan)
Taiga Uno, Semiconductor Leading Edge Technologies, Inc. (Japan)
Takashi Kamo, Semiconductor Leading Edge Technologies, Inc. (Japan)
Kentaro Matsunaga, Semiconductor Leading Edge Technologies, Inc. (Japan)
Daisuke Kawamura, Semiconductor Leading Edge Technologies, Inc. (Japan)
Toshihiko Tanaka, Semiconductor Leading Edge Technologies, Inc. (Japan)
Hiroyuki Tanaka, Semiconductor Leading Edge Technologies, Inc. (Japan)
Shuichi Saito, Semiconductor Leading Edge Technologies, Inc. (Japan)
Ichiro Mori, Semiconductor Leading Edge Technologies, Inc. (Japan)


Published in SPIE Proceedings Vol. 7636:
Extreme Ultraviolet (EUV) Lithography
Bruno M. La Fontaine, Editor(s)

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