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Proceedings Paper

Fabrication of 35nm via-hole patterns for interconnect test chips with EUV lithography
Author(s): Yuusuke Tanaka; Hajime Aoyama; Kazuo Tawarayama; Shunko Magoshi; Daisuke Kawamura; Kentaro Matsunaga; Takashi Kamo; Yukiyasu Arisawa; Taiga Uno; Hiroyuki Tanaka; Naofumi Nakamura; Eiichi Soda; Noriaki Oda; Shuichi Saito; Ichiro Mori
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Paper Abstract

In the fabrication of interconnect test chips with a half pitch of 35 nm, we used an EUV full-field scanner (EUV1) for three critical layers: Metal 1, Via 1 and Metal 2. In this study, we focused on the Via-1 layer and investigated the printing characteristics of 35-nm via-hole patterns. There are three types of major via-hole patterns; aligned, staggered, and isolated. Simple optical proximity effect correction (OPC) and shadowing effect correction (SEC) were applied to the mask patterns to reduce the iso-dense bias and anisotropy of hole shapes. Mask critical-dimension (CD) correction enabled the fabrication of all three types of patterns with almost the same CD. A simulation analysis revealed the mask error enhancement factor (MEEF) to be about 2.5, the exposure latitude to be about 18%, and the depth of focus (DOF) to be about 100 nm for 35-nm via holes when the resist CD was 35 nm. The experimental results agree fairly well with the simulation results. The intra-field CD uniformity of 35-nm via holes is 3.3 nm (3σ). The intra-field overlay accuracy (Mean+3σ) between the Via-1 and Metal-2 layers is better than 15 nm. We used a multi-stacked resist to fabricate 35-nm via holes in a low-k dielectric layer. Moreover, we fabricated interconnect test chips and measured their electrical properties. The resistance of 32-nm vias is 12.4Ω, which meets the target of International Technology Roadmap for Semiconductors (ITRS). The yield of 40k dense via chains was over 70%. The results demonstrate that EUV lithography is useful for the fabrication of ULSI devices with a half pitch of 35 nm and beyond.

Paper Details

Date Published: 22 March 2010
PDF: 12 pages
Proc. SPIE 7636, Extreme Ultraviolet (EUV) Lithography, 76362D (22 March 2010); doi: 10.1117/12.846315
Show Author Affiliations
Yuusuke Tanaka, Semiconductor Leading Edge Technologies, Inc. (Japan)
Hajime Aoyama, Semiconductor Leading Edge Technologies, Inc. (Japan)
Kazuo Tawarayama, Semiconductor Leading Edge Technologies, Inc. (Japan)
Shunko Magoshi, Semiconductor Leading Edge Technologies, Inc. (Japan)
Daisuke Kawamura, Semiconductor Leading Edge Technologies, Inc. (Japan)
Kentaro Matsunaga, Semiconductor Leading Edge Technologies, Inc. (Japan)
Takashi Kamo, Semiconductor Leading Edge Technologies, Inc. (Japan)
Yukiyasu Arisawa, Semiconductor Leading Edge Technologies, Inc. (Japan)
Taiga Uno, Semiconductor Leading Edge Technologies, Inc. (Japan)
Hiroyuki Tanaka, Semiconductor Leading Edge Technologies, Inc. (Japan)
Naofumi Nakamura, Semiconductor Leading Edge Technologies, Inc. (Japan)
Eiichi Soda, Semiconductor Leading Edge Technologies, Inc. (Japan)
Noriaki Oda, Semiconductor Leading Edge Technologies, Inc. (Japan)
Shuichi Saito, Semiconductor Leading Edge Technologies, Inc. (Japan)
Ichiro Mori, Semiconductor Leading Edge Technologies, Inc. (Japan)


Published in SPIE Proceedings Vol. 7636:
Extreme Ultraviolet (EUV) Lithography
Bruno M. La Fontaine, Editor(s)

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