Share Email Print

Proceedings Paper

Challenges for low-k1 lithography in logic devices by source mask co-optimization
Author(s): Kazuyuki Yoshimochi; Seiji Nagahara; Kazuhiro Takeda; Takayuki Uchiyama
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

Through simulation and experiment, we evaluate the performance of process window improvement by source only optimization, mask only optimization or source mask co-optimization. From the results, we demonstrate that SMO is the most effective, and free-form source application is also effective. Additionally, it is found that SMO with calibrated resist model is very predictable. We then show that SMO application provides reasonable process window for 28-nm node and 22-nm node.

Paper Details

Date Published: 10 March 2010
PDF: 11 pages
Proc. SPIE 7640, Optical Microlithography XXIII, 76401K (10 March 2010); doi: 10.1117/12.846263
Show Author Affiliations
Kazuyuki Yoshimochi, NEC Electronics Corp. (Japan)
Seiji Nagahara, NEC Electronics Corp. (Japan)
Kazuhiro Takeda, NEC Electronics Corp. (Japan)
Takayuki Uchiyama, NEC Electronics Corp. (Japan)

Published in SPIE Proceedings Vol. 7640:
Optical Microlithography XXIII
Mircea V. Dusa; Will Conley, Editor(s)

© SPIE. Terms of Use
Back to Top