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Proceedings Paper

The important challenge to extend spacer DP process towards 22nm and beyond
Author(s): Kenichi Oyama; Eiichi Nishimura; Masato Kushibiki; Kazuhide Hasebe; Shigeru Nakajima; Hiroki Murakami; Arisa Hara; Shohei Yamauchi; Sakurako Natori; Kazuo Yabe; Tomohito Yamaji; Ryota Nakatsuji; Hidetami Yaegashi
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Paper Abstract

Double patterning processes are techniques that can be used to form etching mask patterns for 32nm node and possibly for 22nm node as well. The self-aligned spacer process has drawn much attention as an effective means of enabling the formation of repetitive patterns. The self-aligned spacer process is now being used in actual device manufacturing, but it has many process steps driving up process cost while also assuming a 1D pattern. This paper demonstrates extensions of the self-aligned spacer process by an enhanced 2D positive spacer process and a newly developed spacer DP process using a 1D negative spacer.

Paper Details

Date Published: 26 March 2010
PDF: 6 pages
Proc. SPIE 7639, Advances in Resist Materials and Processing Technology XXVII, 763907 (26 March 2010); doi: 10.1117/12.845970
Show Author Affiliations
Kenichi Oyama, Tokyo Electron Ltd. (Japan)
Eiichi Nishimura, Tokyo Electron AT Ltd. (Japan)
Masato Kushibiki, Tokyo Electron AT Ltd. (Japan)
Kazuhide Hasebe, Tokyo Electron TOHOKU Ltd. (Japan)
Shigeru Nakajima, Tokyo Electron TOHOKU Ltd. (Japan)
Hiroki Murakami, Tokyo Electron TOHOKU Ltd. (Japan)
Arisa Hara, Tokyo Electron Ltd. (Japan)
Shohei Yamauchi, Tokyo Electron Ltd. (Japan)
Sakurako Natori, Tokyo Electron Ltd. (Japan)
Kazuo Yabe, Tokyo Electron Ltd. (Japan)
Tomohito Yamaji, Tokyo Electron Ltd. (Japan)
Ryota Nakatsuji, Tokyo Electron Ltd. (Japan)
Hidetami Yaegashi, Tokyo Electron Ltd. (Japan)


Published in SPIE Proceedings Vol. 7639:
Advances in Resist Materials and Processing Technology XXVII
Robert D. Allen, Editor(s)

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