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Proceedings Paper

Design of analog-type high-speed SerDes using digital components for optical chip-to-chip link
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Paper Abstract

An analog-type high-speed serializer/deserializer (SerDes) has been designed for optical links especially between CPU and memory. The circuit uses a system clock and its phases to multiplex data to the serial link which avoids the need for a PLL-based high frequency clock generation used in serializing parallel data as in conventional SerDes design. The multiplexed link combined with the de-serializing clock is used as a reference signal for de-serialization. The SerDes is being designed in a 0.13 μm Si-CMOS technology. The fabricated serializer has a core chip size of 360 x750 μm2. Power dissipation for the SerDes is 71.4 mW operating up to 6.5 Gbps.

Paper Details

Date Published: 23 February 2010
PDF: 9 pages
Proc. SPIE 7607, Optoelectronic Interconnects and Component Integration IX, 76071B (23 February 2010); doi: 10.1117/12.843063
Show Author Affiliations
Jamshid Sangirov, Korea Advanced Institute of Science and Technology (Korea, Republic of)
Nga T. H. Nguyen, Korea Advanced Institute of Science and Technology (Korea, Republic of)
Trong-Hieu Ngo, Korea Advanced Institute of Science and Technology (Korea, Republic of)
Dong-min Im, Korea Advanced Institute of Science and Technology (Korea, Republic of)
Augustine I. Ukaegbu, Korea Advanced Institute of Science and Technology (Korea, Republic of)
Tae-Woo Lee, Korea Advanced Institute of Science and Technology (Korea, Republic of)
Mu Hee Cho, Korea Advanced Institute of Science and Technology (Korea, Republic of)
Hyo-Hoon Park, Korea Advanced Institute of Science and Technology (Korea, Republic of)


Published in SPIE Proceedings Vol. 7607:
Optoelectronic Interconnects and Component Integration IX
Alexei L. Glebov; Ray T. Chen, Editor(s)

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