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Proceedings Paper

Optimization of alignment/overlay sampling and marker layout to improve overlay performance for double patterning technology
Author(s): Chuei-Fu Chue; Tsann-Bim Chiou; Chun-Yen Huang; Alek C. Chen; Chiang-Lin Shih
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Paper Abstract

Double patterning technology is capable of extending usability of immersion ArF systems for 32nm half-pitch node and below. However, overlay errors between the two patterning steps will directly contribute to critical dimension variation in a dual litho-etch process. The overlay errors need to be reduced significantly to meet the tight critical dimension uniformity requirement in the technology nodes. The present scanners are able to correct intra- and inter-field overlay errors that include not only linear terms but also certain higher-order terms. As a result, a 3nm overlay requirement for DPT becomes feasible by applying the most advanced correction schemes. Overlay modeling with a larger number of sample fields will give a more accurate estimate of the model parameters and will therefore improve the overlay corrections; however, metrology time will increase simultaneously. To balance the correction accuracy and metrology time, the number of fields and its layout on the wafer must be optimized. This also applies to wafer alignment, one of the other factors that determine the overlay performance. A bad alignment sampling scheme will cause a poor overlay performance in the end. Increasing the number of sample fields can improve the alignment performance but wafer throughput will be impacted immediately. Performance of the intra-field correction is dependent on number and distribution of the markers within an exposure field. Correction per field, for instance, is one of the most effective correction schemes. However, it needs to measure extra markers in each field for overlay modeling especially when including high-order terms. To limit the chip area occupied by the markers and the metrology time, it is necessary to well control the number of the markers. Moreover, accuracy of the overlay models is sensitive to layout of the markers. The overlay marker layout hence needs to be optimized to gain a robust correction with a minimum number of markers. In this paper, firstly we developed various geometry-based sampling methods for both alignment and overlay corrections to evaluate correction robustness while keeping the number of sample fields as small as possible. The results show that modeling with a limited number of fields can adequately describe a full-wafer alignment/overlay signature and the errors can be well corrected accordingly. A hybrid sampling approach was then proposed taking into consideration the spatial coverage (geometry-based) as well as the overlay signature of the fields. To improve the intra-field correction, an algorithm to assist in designing the layout of the overlay markers on a mask was developed. The most effective marker layouts with the least number of markers were suggested for different correction schemes. Using the most effective correction scheme as well as the proposed optimization techniques, the overlay performance can be improved to meet the overlay requirement of the 32nm DPT.

Paper Details

Date Published: 11 December 2009
PDF: 12 pages
Proc. SPIE 7520, Lithography Asia 2009, 75200G (11 December 2009); doi: 10.1117/12.837137
Show Author Affiliations
Chuei-Fu Chue, Nanya Technology Corp. (Taiwan)
Tsann-Bim Chiou, ASML TDC Asia (Taiwan)
Chun-Yen Huang, Nanya Technology Corp. (Taiwan)
Alek C. Chen, ASML TDC Asia (Taiwan)
Chiang-Lin Shih, Nanya Technology Corp. (Taiwan)


Published in SPIE Proceedings Vol. 7520:
Lithography Asia 2009
Alek C. Chen; Woo-Sung Han; Burn J. Lin; Anthony Yen, Editor(s)

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