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Proceedings Paper

Design of low latency clock distribution network for long linear photo detector readout circuit
Author(s): Yang Tai; Yiqiang Zhao
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Paper Abstract

Digital clock network design becomes one of the key research topics with the circuit area and the operation frequence increased. In order to improve the performance of the long linear arrays photo detector (512 elements) readout circuit and reduce the control timing uncertainty, this paper presented an improved clock distribution network based on full-custom design methodology, which optimized the system clock chip distribution. The circuit chip has been fabricated using Chartered 0.35um CMOS process, and the chip size was 3*18mm2, which operated at 50MHz. Test results showed that the improved clock distribution network can effectively reduce the clock delay for more than 87% and had a good inter-channel consistency. The readout accuracy met the design requirements.

Paper Details

Date Published: 6 August 2009
PDF: 7 pages
Proc. SPIE 7384, International Symposium on Photoelectronic Detection and Imaging 2009: Advances in Imaging Detectors and Applications, 738431 (6 August 2009); doi: 10.1117/12.837133
Show Author Affiliations
Yang Tai, Tianjin Univ. (China)
Yiqiang Zhao, Tianjin Univ. (China)


Published in SPIE Proceedings Vol. 7384:
International Symposium on Photoelectronic Detection and Imaging 2009: Advances in Imaging Detectors and Applications
Kun Zhang; Xiang-jun Wang; Guang-jun Zhang; Ke-cong Ai, Editor(s)

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