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Proceedings Paper

Novel integrated readout circuit of variable integration time with background suppression for quantum dot infrared photo-detectors
Author(s): Yi-Chuan Lu; Hsiu-Li Shieh; Sen-Chuan Hung; Tai-Ping Sun; Meng-Lieh Sheu; Shiang-Feng Tang; Cheng-Der Chiang
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Paper Abstract

This paper discussed about a readout circuit for Quantum Dot Infrared Photodetector (QDIP) Focal-Plane-Array (FPA) imaging system. The readout circuit employed a modified regulated cascode circuit to stabilize the bias of QDIP. The readout circuit consisted of in-pixel dark current cancellation circuit, sensed current integration and in-pixel switch integration capacitor. The chip worked at 5V power supply and operated at 1MHz clock rate. Output voltage ranging from 2 volt to 4 volt was generated when the sensing current from 10nA to 100nA, the dark current was set up to 100nA. The total power consumption was less than 3.3 mW. The dimension of unit pixel was 30×30μm and the integration capacitance was about 0.24pF. The 8×8 pixels array readout circuit of in-pixel variable integration capacitors was implemented by using TSMC 0.35μm Mixed Signal 2P4M CMOS process.

Paper Details

Date Published: 5 August 2009
PDF: 10 pages
Proc. SPIE 7383, International Symposium on Photoelectronic Detection and Imaging 2009: Advances in Infrared Imaging and Applications, 73833F (5 August 2009); doi: 10.1117/12.835587
Show Author Affiliations
Yi-Chuan Lu, National Chi Nan Univ. (Taiwan)
Hsiu-Li Shieh, National Chi Nan Univ. (Taiwan)
Sen-Chuan Hung, National Chi Nan Univ. (Taiwan)
Tai-Ping Sun, National Chi Nan Univ. (Taiwan)
Meng-Lieh Sheu, National Chi Nan Univ. (Taiwan)
Shiang-Feng Tang, Chungshan Institute of Science & Technology (Taiwan)
Cheng-Der Chiang, Chungshan Institute of Science & Technology (Taiwan)


Published in SPIE Proceedings Vol. 7383:
International Symposium on Photoelectronic Detection and Imaging 2009: Advances in Infrared Imaging and Applications
Jeffery Puschell; Hai-mei Gong; Yi Cai; Jin Lu; Jin-dong Fei, Editor(s)

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