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Proceedings Paper

Automated optimization of look-up table implementation for function evaluation on FPGAs
Author(s): L. Deng; C. Chakrabarti; N. Pitsianis; X. Sun
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Paper Abstract

This paper presents a systematic approach for automatic generation of look-up-table (LUT) for function evaluations and minimization in hardware resource on field programmable gate arrays (FPGAs). The class of functions supported by this approach includes sine, cosine, exponentials, Gaussians, the central B-splines, and certain cylinder functions that are frequently used in applications for signal and image processing and data processing. In order to meet customer requirements in accuracy and speed as well as constraints on the use of area and on-chip memory, the function evaluation is based on numerical approximation with Taylor polynomials. Customized data precisions are supported in both fixed point and floating point representations. The optimization procedure involves a search in three-dimensional design space of data precision, sampling density and approximation degree. It utilizes both model-based estimates and gradient-based information gathered during the search. The approach was tested with actual synthesis results on the Xilinx Virtex-2Pro FPGA platform.

Paper Details

Date Published: 2 September 2009
PDF: 9 pages
Proc. SPIE 7444, Mathematics for Signal and Information Processing, 744413 (2 September 2009); doi: 10.1117/12.834184
Show Author Affiliations
L. Deng, Arizona State Univ. (United States)
C. Chakrabarti, Arizona State Univ. (United States)
N. Pitsianis, Duke Univ. (United States)
Aristotle Univ. of Thessaloniki (Greece)
X. Sun, Duke Univ. (United States)


Published in SPIE Proceedings Vol. 7444:
Mathematics for Signal and Information Processing
Franklin T. Luk; Mark S. Schmalz; Gerhard X. Ritter; Junior Barrera; Jaakko T. Astola, Editor(s)

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