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Proceedings Paper

Fundamental performance differences between CMOS and CCD imagers: part III
Author(s): James Janesick; Jeff Pinter; Robert Potter; Tom Elliott; James Andrews; John Tower; John Cheng; Jeanne Bishop
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Paper Abstract

This paper is a status report on recent scientific CMOS imager developments since when previous publications were written. Focus today is being given on CMOS design and process optimization because fundamental problems affecting performance are now reasonably well understood. Topics found in this paper include discussions on a low cost custom scientific CMOS fabrication approach, substrate bias for deep depletion imagers, near IR and x-ray point-spread performance, custom fabricated high resisitivity epitaxial and SOI silicon wafers for backside illuminated imagers, buried channel MOSFETs for ultra low noise performance, 1 e- charge transfer imagers, high speed transfer pixels, RTS/ flicker noise versus MOSFET geometry, pixel offset and gain non uniformity measurements, high S/N dCDS/aCDS signal processors, pixel thermal dark current sources, radiation damage topics, CCDs fabricated in CMOS and future large CMOS imagers planned at Sarnoff.

Paper Details

Date Published: 17 September 2009
PDF: 26 pages
Proc. SPIE 7439, Astronomical and Space Optical Systems, 743907 (17 September 2009); doi: 10.1117/12.831203
Show Author Affiliations
James Janesick, Sarnoff Corp. (United States)
Jeff Pinter, Sarnoff Corp. (United States)
Robert Potter, Sarnoff Corp. (United States)
Tom Elliott, Jet Propulsion Lab. (United States)
James Andrews, Sarnoff Corp. (United States)
John Tower, Sarnoff Corp. (United States)
John Cheng, Chronicle Technology Inc. (United States)
Jeanne Bishop, Chronicle Technology Inc. (United States)

Published in SPIE Proceedings Vol. 7439:
Astronomical and Space Optical Systems
Penny G. Warren; James B. Heaney; Robert K. Tyson; Michael Hart; E. Todd Kvamme; Cheryl J. Marshall, Editor(s)

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