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Proceedings Paper

On the design of a radix-10 online floating-point multiplier
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Paper Abstract

This paper describes an approach to design and implement a radix-10 online floating-point multiplier. An online approach is considered because it offers computational flexibility not available with conventional arithmetic. The design was coded in VHDL and compiled, synthesized, and mapped onto a Virtex 5 FPGA to measure cost in terms of LUTs (look-up-tables) as well as the cycle time and total latency. The routing delay which was not optimized is the major component in the cycle time. For a rough estimate of the cost/latency characteristics, our design was compared to a standard radix-2 floating-point multiplier of equivalent precision. The results demonstrate that even an unoptimized radix-10 online design is an attractive implementation alternative for FPGA floating-point multiplication.

Paper Details

Date Published: 3 September 2009
PDF: 8 pages
Proc. SPIE 7444, Mathematics for Signal and Information Processing, 74440P (3 September 2009); doi: 10.1117/12.826754
Show Author Affiliations
Robert D. McIlhenny, California State Univ., Northridge (United States)
Milos D. Ercegovac, Univ. of California, Los Angeles (United States)


Published in SPIE Proceedings Vol. 7444:
Mathematics for Signal and Information Processing
Franklin T. Luk; Mark S. Schmalz; Gerhard X. Ritter; Junior Barrera; Jaakko T. Astola, Editor(s)

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