Share Email Print
cover

Proceedings Paper

VLSI architecture of wavelet transform based on basic lifting elements
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

In this paper, we propose a lifting architecture based on a basic lifting unit, whose structure performs lifting operations in a repetitive way. By analyzing computational processes in lifting in detail, the reusable Basic Lifting Element (BLE) is presented. The BLE structure is designed and optimized from the viewpoint of hardware implementation. The proposed lifting processor can be executed by arranging BLEs repeatedly. Experimental results show that the proposed architecture can transform any size of tiles with 9/7 filter and 5/3 filter for lossy and lossless compression, respectively. The lifting processor is designed in Verilog HDL and synthesized into Xilinx FPGA, which can run up to 130MHz.

Paper Details

Date Published: 31 August 2009
PDF: 9 pages
Proc. SPIE 7455, Satellite Data Compression, Communication, and Processing V, 74550E (31 August 2009); doi: 10.1117/12.825222
Show Author Affiliations
Jie Guo, Xidian Univ. (China)
Yunsong Li, Xidian Univ. (China)
Keyan Wang, Xidian Univ. (China)
Chengke Wu, Xidian Univ. (China)


Published in SPIE Proceedings Vol. 7455:
Satellite Data Compression, Communication, and Processing V
Bormin Huang; Antonio J. Plaza; Raffaele Vitulli, Editor(s)

© SPIE. Terms of Use
Back to Top