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Proceedings Paper

A study of mask inspection method with pattern priority and printability check
Author(s): Masakazu Tokita; Hideo Tsuchiya; Takafumi Inoue; Tadao Inoue; Masaki Yamabe
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Paper Abstract

The cost of mask is increasing dramatically along with the continuous semiconductor scaling. ASET started a 4-year project to reduce mask manufacturing cost and TAT by optimizing Mask Data Preparation (MDP), mask writing, and mask inspection in 2006, with the support from the New Energy and Industrial Technology Development Organization (NEDO). Concerning the mask inspection, the project aims at shortening the review time after inspection. In mask inspection it approaches the limit to inspect the entire surface of a mask in the unique defect judgment algorithm without a pseudo defect. In addition, a nuisance defect including a pseudo defect increases by raising the defect detection sensitivity, and the review time after inspection increases. Mask inspection total time increases too and this will raise the mask inspection cost. Practical mask inspection can be conducted now by inputting the judgment level based on directions of design data there and by making a defect judgment level of every domestic area changeable. We can also shorten the review time by analyzing the printability on the wafer of the detected defect by the simulation, and by using the result for the defect judgment. In this report, we will show the latest research result about an inspection system technology that the defect judgment level for each domestic area can be changed, and a method to input the defect judgment level based on the pattern importance, which a device designer intended, into inspection equipment. In addition, we will show a design of the interface technology that hand over the information of the detected defect to a process simulator (wafer image simulator).

Paper Details

Date Published: 11 May 2009
PDF: 9 pages
Proc. SPIE 7379, Photomask and Next-Generation Lithography Mask Technology XVI, 73792A (11 May 2009); doi: 10.1117/12.824324
Show Author Affiliations
Masakazu Tokita, Association of Super-Advanced Electronics Technologies (Japan)
Hideo Tsuchiya, Association of Super-Advanced Electronics Technologies (Japan)
Takafumi Inoue, Association of Super-Advanced Electronics Technologies (Japan)
Tadao Inoue, Association of Super-Advanced Electronics Technologies (Japan)
Masaki Yamabe, Association of Super-Advanced Electronics Technologies (Japan)


Published in SPIE Proceedings Vol. 7379:
Photomask and Next-Generation Lithography Mask Technology XVI
Kunihiro Hosono, Editor(s)

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