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Proceedings Paper

Enabling accurate gate profile control with inline 3D-AFM
Author(s): Tianming Bao; Andrew Lopez; Dean Dawson
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Paper Abstract

The logic and memory semiconductor device technology strives to follow the aggressive ITRS roadmap. The ITRS calls for increased 3D metrology to meet the demand for tighter process control at 45nm and 32nm nodes. In particular, gate engineering has advanced to a level where conventional metrology by CD-SEM and optical scatterometry (OCD) faces fundamental limitations without involvement of 3D atomic force microscope (3D-AFM or CD-AFM). This paper reports recent progress in 3D-AFM to address the metrology need to control gate dimension in MOSFET transistor formation. 3D-AFM metrology measures the gate electrode at post-etch with the lowest measurement uncertainty for critical gate geometry, including linewidth, sidewall profile, sidewall angle (SWA), line width roughness (LWR), and line edge roughness (LER). 3D-AFM enables accurate gate profile control in three types of metrology applications: reference metrology to validate CD-SEM and OCD, inline depth or 3D monitoring, or replacing TEM for 3D characterization for engineering analysis.

Paper Details

Date Published: 22 May 2009
PDF: 8 pages
Proc. SPIE 7378, Scanning Microscopy 2009, 73781G (22 May 2009); doi: 10.1117/12.824203
Show Author Affiliations
Tianming Bao, Veeco Instruments Inc. (United States)
Andrew Lopez, Veeco Instruments Inc. (United States)
Dean Dawson, Veeco Instruments Inc. (United States)


Published in SPIE Proceedings Vol. 7378:
Scanning Microscopy 2009
Michael T. Postek; Michael T. Postek; Michael T. Postek; Dale E. Newbury; Dale E. Newbury; Dale E. Newbury; S. Frank Platek; S. Frank Platek; S. Frank Platek; David C. Joy; David C. Joy; David C. Joy, Editor(s)

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