Share Email Print

Proceedings Paper

Dual mode 1.25-2.5 Gb/s CMOS limiting amplifier circuit for optical receivers
Author(s): Cristian M. Albina
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

A 1.25-2.5Gb/s burst-mode limiting amplifier for gigabit passive optical networks (GPON) is presented in this paper. It supports both PIN-PD and APD diodes. A response time of 5 ns and sensitivity of 4 mVpp is achieved by introducing a modified amplified stage with active feedback and negative Miller capacitance compensation techniques. This circuit operates with a supply voltage 3 V and it is fabricated in 180 nm CMOS technology. The influence of the parasitic layout elements and their effects on the performance of the limiting amplifier will be illustrated using RC and RLC parasitic extraction and simulation results.

Paper Details

Date Published: 7 January 2009
PDF: 4 pages
Proc. SPIE 7297, Advanced Topics in Optoelectronics, Microelectronics, and Nanotechnologies IV, 729721 (7 January 2009); doi: 10.1117/12.823685
Show Author Affiliations
Cristian M. Albina, IC Design (Germany)

Published in SPIE Proceedings Vol. 7297:
Advanced Topics in Optoelectronics, Microelectronics, and Nanotechnologies IV
Paul Schiopu; Cornel Panait; George Caruntu; Adrian Manea, Editor(s)

© SPIE. Terms of Use
Back to Top