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Proceedings Paper

A programmable vision chip with high speed image processing
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Paper Abstract

A high speed Analog VLSI Image acquisition and pre-processing system is described in this paper. A 64×64 pixel retina is used to extract the magnitude and direction of spatial gradients from images. So, the sensor implements some lowlevel image processing in a massively parallel strategy in each pixel of the sensor. Spatial gradients, various convolutions as Sobel filter or Laplacian are described and implemented on the circuit. The retina implements in a massively parallel way, at pixel level, some various treatments based on a four-quadrants multipliers architecture. Each pixel includes a photodiode, an amplifier, two storage capacitors and an analog arithmetic unit. A maximal output frame rate of about 10 000 frames per second with only image acquisition and 2000 to 5000 frames per second with image processing is achieved in a 0.35 μm standard CMOS process. The retina provides address-event coded output on three asynchronous buses, one output is dedicated to the gradient and both other to the pixel values. A prototype based on this principle, has been designed. Simulation results from Mentor GraphicsTMsoftware and AustriaMicrosystem Design kit are presented.

Paper Details

Date Published: 10 February 2009
PDF: 10 pages
Proc. SPIE 7126, 28th International Congress on High-Speed Imaging and Photonics, 712619 (10 February 2009); doi: 10.1117/12.822294
Show Author Affiliations
Jérôme Dubois, LCE, Commissariat à l'Energie Atomique Saclay (France)
Michel Paindavoine, Le2i, CNRS, Univ. de Bourgogne (France)
Dominique Ginhac, Le2i, CNRS, Univ. de Bourgogne (France)


Published in SPIE Proceedings Vol. 7126:
28th International Congress on High-Speed Imaging and Photonics
Harald Kleine; Martha Patricia Butron Guillen, Editor(s)

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