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Proceedings Paper

Using partial reconfiguration for SoC design and implementation
Author(s): Yana E. Krasteva; Jorge Portilla; Félix Tobajas Guerrero; Eduardo de la Torre
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Paper Abstract

Most reconfigurable systems rely on FPGA technology. Among these ones, those which permit dynamic and partial reconfiguration, offer added benefits in flexibility, in-field device upgrade, improved design and manufacturing time, and even, in some cases, power consumption reductions. However, dynamic reconfiguration is a complex task, and the real benefits of its use in real applications have been often questioned. This paper presents an overview of the partial reconfiguration technique application, along with four original applications. The main goal of these applications is to test several architectures with different flexibility and, to search for the partial reconfiguration "killing application", that is, the application that better demonstrates the benefits of today reconfigurable systems based on commercial FPGAs. Therefore, the presented applications are rather a proof of concept, than fully operative and closed systems. First, a brief introduction to the partial reconfigurable systems application topic has been included. After that, the descriptions of the created reconfigurable systems are presented: first, an on-chip communications emulation framework, second, an on chip debugging system, third, a wireless sensor network reconfigurable node and finally, a remote reconfigurable client-server device. Each application is described in a separate section of the paper along with some test and results. General conclusions are included at the end of the paper.

Paper Details

Date Published: 28 May 2009
PDF: 12 pages
Proc. SPIE 7363, VLSI Circuits and Systems IV, 736306 (28 May 2009); doi: 10.1117/12.821718
Show Author Affiliations
Yana E. Krasteva, Univ. Politécnica de Madrid (Spain)
Jorge Portilla, Univ. Politécnica de Madrid (Spain)
Félix Tobajas Guerrero, Univ. de Las Palmas de Gran Canaria (Spain)
Eduardo de la Torre, Univ. Politécnica de Madrid (Spain)


Published in SPIE Proceedings Vol. 7363:
VLSI Circuits and Systems IV
Teresa Riesgo; Eduardo de la Torre; Leandro Soares Indrusiak, Editor(s)

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