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Proceedings Paper

Automated insertion of twin gates to improve reliability concerning gate oxide breakdown
Author(s): Hagen Saemrow; Claas Cornelius; Frank Sill; Andreas Tockhorn; Dirk Timmermann
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Paper Abstract

Scaling device dimensions towards atomic scales leads to increased reliability and yield concerns which considerably affects the work of integrated circuit designers. Furthermore, the complexity of integrated systems increases which leads to a demand for tool assisted reliability insertion during the design process. Lots of research efforts have focused on softerrors and system-level approaches. However, only few low-level solutions have been published to enhance lifetime reliability. Investigations in this field have reached an up to 200 % increased reliability concerning gate oxide breakdown if so called Twin Gates have been inserted. This contribution comprehensively presents algorithms to implement these redundant cells automatically during logic synthesis. Besides the placement in the whole design process, approaches are provided to insert Twin Gates correctly considering timing and area issues.

Paper Details

Date Published: 28 May 2009
PDF: 8 pages
Proc. SPIE 7363, VLSI Circuits and Systems IV, 736310 (28 May 2009); doi: 10.1117/12.821711
Show Author Affiliations
Hagen Saemrow, Univ. of Rostock (Germany)
Claas Cornelius, Univ. of Rostock (Germany)
Frank Sill, Federal Univ. of Minas Gerais (Brazil)
Andreas Tockhorn, Univ. of Rostock (Germany)
Dirk Timmermann, Univ. of Rostock (Germany)

Published in SPIE Proceedings Vol. 7363:
VLSI Circuits and Systems IV
Teresa Riesgo; Eduardo de la Torre; Leandro Soares Indrusiak, Editor(s)

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