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Proceedings Paper

Dynamic power management of network-on-chip
Author(s): Stefano Gigli; Luca Casagrande Montesi; Andrea Primavera; Massimo Conti
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Paper Abstract

Systems on Chip performances in terms of speed and power dissipation is becoming dominated by communication between the cores. To overcome the limitations of traditional bus architectures, nowadays Network-on-Chip architectures are adopted. The Dynamic Power Management architecture and algorithm and Network-on-Chip topology and routing algorithms should be selected considering that they both effect in a complex and complementary way the network throughput and power dissipation. This paper presents the analysis of the effect of Dynamic Power Management strategies on Network-on-Chip performances.

Paper Details

Date Published: 28 May 2009
PDF: 11 pages
Proc. SPIE 7363, VLSI Circuits and Systems IV, 73630O (28 May 2009); doi: 10.1117/12.821665
Show Author Affiliations
Stefano Gigli, Univ. Politecnica delle Marche (Italy)
Luca Casagrande Montesi, Univ. Politecnica delle Marche (Italy)
Andrea Primavera, Univ. Politecnica delle Marche (Italy)
Massimo Conti, Univ. Politecnica delle Marche (Italy)


Published in SPIE Proceedings Vol. 7363:
VLSI Circuits and Systems IV
Teresa Riesgo; Eduardo de la Torre; Leandro Soares Indrusiak, Editor(s)

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