Share Email Print
cover

Proceedings Paper

ESL flow for a hardware H.264/AVC decoder using TLM-2.0 and high level synthesis: a quantitative study
Author(s): M. Thadani; P. P. Carballo; P. Hernández; G. Marrero; A. Núñez
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

The present paper describes an Electronic System Level (ESL) design methodology which was established and employed in the creation of a H.264/AVC baseline decoder. The methodology involves the synthesis of the algorithmic description of the functional blocks that comprise the decoder, using a high level synthesis tool. Optimization and design space exploration is carried out at the algorithmic level before performing logic synthesis. Final, post-place and route implementation results show that the decoder can operate at the target frequency of 100 MHz and meet real time requirements for QCIF frames.

Paper Details

Date Published: 28 May 2009
PDF: 12 pages
Proc. SPIE 7363, VLSI Circuits and Systems IV, 73630K (28 May 2009); doi: 10.1117/12.821647
Show Author Affiliations
M. Thadani, Univ. de Las Palmas de Gran Canaria (Spain)
P. P. Carballo, Univ. de Las Palmas de Gran Canaria (Spain)
P. Hernández, Univ. de Las Palmas de Gran Canaria (Spain)
G. Marrero, Univ. de Las Palmas de Gran Canaria (Spain)
A. Núñez, Univ. de Las Palmas de Gran Canaria (Spain)


Published in SPIE Proceedings Vol. 7363:
VLSI Circuits and Systems IV
Teresa Riesgo; Eduardo de la Torre; Leandro Soares Indrusiak, Editor(s)

© SPIE. Terms of Use
Back to Top