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Proceedings Paper

Analysis of current transients in SRAM memories for single event upset detection
Author(s): G. Torrens; S. Bota; J. Verd; B. Alorda; J. Merino; J. Segura
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Paper Abstract

Soft errors resulting from the impact of charged particles are emerging as a major issue in the design of reliable circuits at deep sub-micron dimensions even at ground level. To face this challenge, a designer must dispose of a variety of mitigation schemes adapted to their specific design constraints. Built In Current Sensors have been proposed as a detection scheme for single event upsets in SRAM. In this paper, Power-Bus current transients in SRAM memories for Single Event Upset Detection have been analyzed in a 65nm CMOS technology. The different types of current roles which are applied during the simulation is discussed. The results show the important contribution of leakage currents in the response of the memory cell to an external event.

Paper Details

Date Published: 28 May 2009
PDF: 11 pages
Proc. SPIE 7363, VLSI Circuits and Systems IV, 73630Z (28 May 2009); doi: 10.1117/12.821476
Show Author Affiliations
G. Torrens, Univ. de les Illes Balears (Spain)
S. Bota, Univ. de les Illes Balears (Spain)
J. Verd, Univ. de les Illes Balears (Spain)
B. Alorda, Univ. de les Illes Balears (Spain)
J. Merino, Univ. de les Illes Balears (Spain)
J. Segura, Univ. de les Illes Balears (Spain)


Published in SPIE Proceedings Vol. 7363:
VLSI Circuits and Systems IV
Teresa Riesgo; Eduardo de la Torre; Leandro Soares Indrusiak, Editor(s)

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