The challenges for the next generation of integrated circuit design of analogue and mixed-signal building blocks in standard CMOS technologies for signal conversion demand research progress in the emerging scientific fields of device physics and modelling, converter architectures, design automation, quality assurance and cost factor analysis. Estimation of mismatch for analogue building blocks at the conceptual level and the impact on active area is not a straightforward calculation. The proposed design concepts reduce the over-sizing of transistors, compared with the existing methods, with 15 to 20% for the same quality specification. Besides the reduction of the silicon cost also the design time cost for new topologies is reduced considerably. Comparison has been done for current mode converters (ADC and DAC) and focussing on downscaling technologies. The developed method offers an integrated approach on the estimation of architecture performances, yield and IP-reuse. Matching energy remains constant over process generations and will be the limiting factor for current signal processing. The comprehensive understanding of all sources of mismatches and the use of physical based mismatch modelling in the prediction of mismatch errors, more adequate and realistic sizing of all transistors will result in an overall area reduction of analogue IP blocks. For each technology the following design curves are automatically developed: noise curves for a specified signal bandwidth, choice of overdrive voltage versus lambda and output resistance, physical mismatch error modelling on target current levels. The procedural approach shares knowledge of several design curves and speeds up the design time.

Date Published: 28 May 2009
PDF: 10 pages
Proc. SPIE 7363, VLSI Circuits and Systems IV, 73630R (28 May 2009); doi: 10.1117/12.820912

Published in SPIE Proceedings Vol. 7363:
VLSI Circuits and Systems IV
Teresa Riesgo; Eduardo de la Torre; Leandro Soares Indrusiak, Editor(s)