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Proceedings Paper

Hotspot detection and design recommendation using silicon calibrated CMP model
Author(s): Colin Hui; Xian Bin Wang; Haigou Huang; Ushasree Katakamsetty; Laertis Economikos; Mohammed Fayaz; Stephen Greco; Xiang Hua; Subramanian Jayathi; Chi-Min Yuan; Song Li; Vikas Mehrotra; Kuang Han Chen; Tamba Gbondo-Tugbawa; Taber Smith
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Paper Abstract

Chemical Mechanical Polishing (CMP) has been used in the manufacturing process for copper (Cu) damascene process. It is well known that dishing and erosion occur during CMP process, and they strongly depend on metal density and line width. The inherent thickness and topography variations become an increasing concern for today's designs running through advanced process nodes (sub 65nm). Excessive thickness and topography variations can have major impacts on chip yield and performance; as such they need to be accounted for during the design stage. In this paper, we will demonstrate an accurate physics based CMP model and its application for CMP-related hotspot detection. Model based checking capability is most useful to identify highly environment sensitive layouts that are prone to early process window limitation and hence failure. Model based checking as opposed to rule based checking can identify more accurately the weak points in a design and enable designers to provide improved layout for the areas with highest leverage for manufacturability improvement. Further, CMP modeling has the ability to provide information on interlevel effects such as copper puddling from underlying topography that cannot be captured in Design-for- Manufacturing (DfM) recommended rules. The model has been calibrated against the silicon produced with the 45nm process from Common Platform (IBMChartered- Samsung) technology. It is one of the earliest 45nm CMP models available today. We will show that the CMP-related hotspots can often occur around the spaces between analog macros and digital blocks in the SoC designs. With the help of the CMP model-based prediction, the design, the dummy fill or the placement of the blocks can be modified to improve planarity and eliminate CMP-related hotspots. The CMP model can be used to pass design recommendations to designers to improve chip yield and performance.

Paper Details

Date Published: 12 March 2009
PDF: 12 pages
Proc. SPIE 7275, Design for Manufacturability through Design-Process Integration III, 72751R (12 March 2009); doi: 10.1117/12.816556
Show Author Affiliations
Colin Hui, Chartered Semiconductor Manufacturing, Ltd. (Singapore)
Xian Bin Wang, Chartered Semiconductor Manufacturing, Ltd. (Singapore)
Haigou Huang, Chartered Semiconductor Manufacturing, Ltd. (Singapore)
Ushasree Katakamsetty, Chartered Semiconductor Manufacturing, Ltd. (Singapore)
Laertis Economikos, IBM (United States)
Mohammed Fayaz, IBM (United States)
Stephen Greco, IBM (United States)
Xiang Hua, IBM (United States)
Subramanian Jayathi, Freescale Semiconductor, Inc. (United States)
Chi-Min Yuan, Freescale Semiconductor, Inc. (United States)
Song Li, Cadence Design Systems, Inc. (United States)
Vikas Mehrotra, Cadence Design Systems, Inc. (United States)
Kuang Han Chen, Cadence Design Systems, Inc. (United States)
Tamba Gbondo-Tugbawa, Cadence Design Systems, Inc. (United States)
Taber Smith, Cadence Design Systems, Inc. (United States)


Published in SPIE Proceedings Vol. 7275:
Design for Manufacturability through Design-Process Integration III
Vivek K. Singh; Michael L. Rieger, Editor(s)

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