Share Email Print
cover

Proceedings Paper

Variations in timing and leakage power of 45nm library cells due to lithography and stress effects
Author(s): Kayvan Sadra; Mark Terry; Arjun Rajagopal; Robert A. Soper; Donald Kolarik; Tom Aton; Brian Hornung; Rajesh Khamankar; Philippe Hurat; Bala Kasthuri; Yajun Ran; Nishath Verghese
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

We have conducted a study of context-dependent variability for cells in a 45nm library, including both lithography and stress effects, using the Cadence Litho Electrical Analyzer (LEA) software. Here, we present sample data and address a number of questions that arise in such simulations. These questions include identification of stress effects causing context dependence, impact of the number of contexts on the results, and combining lithography-induced variations due to overlay error with context-dependent variations. Results of such simulations can be used to drive a number of corrective and adaptive actions, among them layout modification, cell placement restrictions, or optimal design margin determination.

Paper Details

Date Published: 12 March 2009
PDF: 10 pages
Proc. SPIE 7275, Design for Manufacturability through Design-Process Integration III, 72750K (12 March 2009); doi: 10.1117/12.816485
Show Author Affiliations
Kayvan Sadra, Texas Instruments, Inc. (United States)
Mark Terry, Texas Instruments, Inc. (United States)
Arjun Rajagopal, Texas Instruments, Inc. (United States)
Robert A. Soper, Texas Instruments, Inc. (United States)
Donald Kolarik, Texas Instruments, Inc. (United States)
Tom Aton, Texas Instruments, Inc. (United States)
Brian Hornung, Texas Instruments, Inc. (United States)
Rajesh Khamankar, Texas Instruments, Inc. (United States)
Philippe Hurat, Cadence Design Systems, Inc. (United States)
Bala Kasthuri, Cadence Design Systems, Inc. (United States)
Yajun Ran, Cadence Design Systems, Inc. (United States)
Nishath Verghese, Cadence Design Systems, Inc. (United States)


Published in SPIE Proceedings Vol. 7275:
Design for Manufacturability through Design-Process Integration III
Vivek K. Singh; Michael L. Rieger, Editor(s)

© SPIE. Terms of Use
Back to Top