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Proceedings Paper

General structure for real-time fringe pattern preprocessing and implementation of median filter and average filter on FPGA
Author(s): Wenjing Gao; Kemao Qian; Haixia Wang; Feng Lin; Hock Soon Seah; Lee Sing Cheong
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Paper Abstract

In recent years, many algorithms were proposed for fringe pattern analysis and phase unwrapping including median filter, Fourier transform, windowed Fourier transform and wavelet transforms. However most of them are computationally expensive, which may be a barrier for real-time analysis for fringe pattern. In this paper an FPGA-based system and optimization framework for fringe pattern processing is presented. Median filter and average filter are taken as examples to show the performance of FPGA system over normal PC in real-time fringe pattern processing. The algorithms have been implemented on Celoxica RC340 FPGA development board using Handel-C - a C-like language with inherent parallelism making the full use of FPGA hardware. Furthermore, evaluation and comparison for computation speed are given between FPGA-based system and normal PC to demonstrate high potential of our hardware system in fringe pattern analysis.

Paper Details

Date Published: 3 October 2008
PDF: 8 pages
Proc. SPIE 7155, Ninth International Symposium on Laser Metrology, 71550Q (3 October 2008); doi: 10.1117/12.814525
Show Author Affiliations
Wenjing Gao, Nanyang Technological Univ. (Singapore)
Kemao Qian, Nanyang Technological Univ. (Singapore)
Haixia Wang, Nanyang Technological Univ. (Singapore)
Feng Lin, Nanyang Technological Univ. (Singapore)
Hock Soon Seah, Nanyang Technological Univ. (Singapore)
Lee Sing Cheong, Nanyang Technological Univ. (Singapore)

Published in SPIE Proceedings Vol. 7155:
Ninth International Symposium on Laser Metrology
Chenggen Quan; Anand Asundi, Editor(s)

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