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Proceedings Paper

Demonstration of full-field patterning of 32 nm test chips using EUVL
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Paper Abstract

EUV lithography is considered one of the options for high volume manufacturing (HVM) of 16 nm MPU node devices [1]. The benefits of high k1(~0.5) imaging enable EUVL to simplify the patterning process and ease design rule restrictions. However, EUVL with its unique imaging process - reflective optics and masks, vacuum operation, and lack of pellicle, has several challenges to overcome before being qualified for production. Thus, it is important to demonstrate the capability to integrate EUVL into existing process flows and characterize issues which could hamper yield. A patterning demonstration of Intel's 32 nm test chips using the ADT at IMEC [7] is presented, This test chip was manufactured using processes initially developed with the Intel MET [2-4] as well as masks made by Intel's mask shop [5,6]. The 32 nm node test chips which had a pitch of 112.5 nm at the trench layer, were patterned on the ADT which resulted in a large k1 factor of 1 and consequently, the trench process window was iso-focal with MEEF = 1. It was found that all mask defects detected by a mask pattern inspection tool printed on the wafer and that 90% of these originated from the substrate. We concluded that improvements are needed in mask defects, photospeed of the resist, overlay, and tool throughput of the tool to get better results to enable us to ultimately examine yield.

Paper Details

Date Published: 17 March 2009
PDF: 9 pages
Proc. SPIE 7271, Alternative Lithographic Technologies, 727116 (17 March 2009); doi: 10.1117/12.814436
Show Author Affiliations
Gilroy Vandentop, Intel Corp. (United States)
Manish Chandhok, Intel Corp. (United States)
Ernisse S. Putna, Intel Corp. (United States)
Todd R. Younkin, Intel Corp. (United States)
James S. Clarke, Intel Corp. (United States)
Steven Carson, Intel Corp. (United States)
Alan Myers, Intel Corp. (Belgium)
Michael Leeson, Intel Corp. (Belgium)
Guojing Zhang, Intel Corp. (United States)
Ted Liang, Intel Corp. (United States)
Tetsunori Murachi, Intel Corp. (Japan)

Published in SPIE Proceedings Vol. 7271:
Alternative Lithographic Technologies
Frank M. Schellenberg; Bruno M. La Fontaine, Editor(s)

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