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Proceedings Paper

Optimization of alignment strategy for metal layer on local interconnect integration
Author(s): Jun-Kyu Ahn; Ji-Hyun Ha; Hong-Ik Kim; Jeong-Lyeol Park; Jae-Sung Choi; Tae-Jong Lee
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Paper Abstract

The influence of processing on wafer alignment is becoming an increasingly important issue. We need to improve an overlay accuracy and alignment performance when design rule are reduce. Especially, the alignment of Metal layers gets some process effects, then we should have prepared to prevent alignment error by the wafer loss and reducing throughput. Alignment of Metal 0 layer in the local interconnect integration is much affected by ILD thickness, resist coating process, but also there are effective phase depth. In this paper, new alignment strategy is presented by simulation of stack structure impact on alignment. We are able to accomplish the increase of alignment signal intensity by new alignment strategy. In addition, we can be achieved alignment robustness to process variation for M0 to M0C alignment of local interconnect.

Paper Details

Date Published: 23 March 2009
PDF: 10 pages
Proc. SPIE 7272, Metrology, Inspection, and Process Control for Microlithography XXIII, 727233 (23 March 2009); doi: 10.1117/12.814434
Show Author Affiliations
Jun-Kyu Ahn, MagnaChip Semiconductor, Ltd. (Korea, Republic of)
Ji-Hyun Ha, MagnaChip Semiconductor, Ltd. (Korea, Republic of)
Hong-Ik Kim, MagnaChip Semiconductor, Ltd. (Korea, Republic of)
Jeong-Lyeol Park, MagnaChip Semiconductor, Ltd. (Korea, Republic of)
Jae-Sung Choi, MagnaChip Semiconductor, Ltd. (Korea, Republic of)
Tae-Jong Lee, MagnaChip Semiconductor, Ltd. (Korea, Republic of)


Published in SPIE Proceedings Vol. 7272:
Metrology, Inspection, and Process Control for Microlithography XXIII
John A. Allgair; Christopher J. Raymond, Editor(s)

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