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Proceedings Paper

Systematic defect filtering and data analysis methodology for design based metrology
Author(s): Hyunjo Yang; Jungchan Kim; Taehyeong Lee; Areum Jung; Gyun Yoo; Donggyu Yim; Sungki Park; Toshiaki Hasebe; Masahiro Yamamoto; Jun Cai
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Paper Abstract

Recently several Design Based Metrologies (DBMs) are introduced and being in use for wafer verification. The major applications of DBM are OPC accuracy improvement, DFM feed-back through Process Window Qualification (PWQ) and advanced process control. In general, however, the amount of output data from DBM is normally so large that it is very hard to handle the data for valuable feed-back. In case of PWQ, more than thousands of hot spots are detected on a single chip at the edge of process window. So, it takes much time and labor to review and analyze all the hot spots detected at PWQ. Design-related systematic defects, however, will be found repeatedly and if they can be classified into groups, it would be possible to save a lot of time for the analysis. We have demonstrated an EDA tool which can handle the large amount of output data from DBM by reducing pattern defects to groups. It can classify millions of patterns into less than thousands of pattern groups. It has been evaluated on the analysis of PWQ of metal layer in NAND Flash memory device and random contact hole patterns in a DRAM device. The result shows that this EDA tool can handle the CD measurement data easily and can save us a lot of time and labor for the analysis. The procedures of systematic defect filtering and data handling using an EDA tool are presented in detail

Paper Details

Date Published: 23 March 2009
PDF: 8 pages
Proc. SPIE 7272, Metrology, Inspection, and Process Control for Microlithography XXIII, 72721C (23 March 2009); doi: 10.1117/12.814373
Show Author Affiliations
Hyunjo Yang, Hynix Semiconductor Inc. (Korea, Republic of)
Jungchan Kim, Hynix Semiconductor Inc. (Korea, Republic of)
Taehyeong Lee, Hynix Semiconductor Inc. (Korea, Republic of)
Areum Jung, Hynix Semiconductor Inc. (Korea, Republic of)
Gyun Yoo, Hynix Semiconductor Inc. (Korea, Republic of)
Donggyu Yim, Hynix Semiconductor Inc. (Korea, Republic of)
Sungki Park, Hynix Semiconductor Inc. (Korea, Republic of)
Toshiaki Hasebe, NanoGeometry Research, Inc. (Japan)
Masahiro Yamamoto, NanoGeometry Research, Inc. (Japan)
Jun Cai, Anchor Semiconductor, Inc. (United States)


Published in SPIE Proceedings Vol. 7272:
Metrology, Inspection, and Process Control for Microlithography XXIII
John A. Allgair; Christopher J. Raymond, Editor(s)

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