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Proceedings Paper

On the integration of memristors with CMOS using nanoimprint lithography
Author(s): Qiangfei Xia; W. M. Tong; W. Wu; J. J. Yang; X. Li; W. Robinett; T. Cardinali; M. Cumbie; J. E. Ellenson; P. Kuekes; R. S. Williams
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Paper Abstract

Memristors were vertically integrated with CMOS circuits using nanoimprint lithography (NIL), making a transistor/memeristor hybrid circuit. Several planarization technologies were developed for the CMOS substrates to meet the surface planarity requirement for NIL. Accordingly, different integration schemes were developed and optimized. UV-curable NIL (UV-NIL) using a double layer spin-on resists was carried out to pattern the electrodes for memristors. This is the first demonstration of NIL on active CMOS substrates that are fabricated in a CMOS fab. Our work demonstrates that NIL is compatible with commercial IC fabrication process. It was also demonstrated that the memristors are integratable with traditional CMOS to make hybrid circuits without changing the current infrastructure in IC industry.

Paper Details

Date Published: 18 March 2009
PDF: 11 pages
Proc. SPIE 7271, Alternative Lithographic Technologies, 727106 (18 March 2009); doi: 10.1117/12.814327
Show Author Affiliations
Qiangfei Xia, Hewlett-Packard Labs. (United States)
W. M. Tong, Hewlett-Packard Labs. (United States)
Hewlett Packard Co. (United States)
W. Wu, Hewlett-Packard Labs. (United States)
J. J. Yang, Hewlett-Packard Labs. (United States)
X. Li, Hewlett-Packard Labs. (United States)
W. Robinett, Hewlett-Packard Labs. (United States)
T. Cardinali, Hewlett-Packard Co. (United States)
M. Cumbie, Hewlett-Packard Co. (United States)
J. E. Ellenson, Hewlett-Packard Co. (United States)
P. Kuekes, Hewlett-Packard Labs. (United States)
R. S. Williams, Hewlett-Packard Labs. (United States)


Published in SPIE Proceedings Vol. 7271:
Alternative Lithographic Technologies
Frank M. Schellenberg; Bruno M. La Fontaine, Editor(s)

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