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Proceedings Paper

Computational technology scaling from 32 nm to 28 and 22 nm through systematic layout printability verification
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Paper Abstract

In this work, we present a novel application of layout printability verification (LPV) to assess the scalability of physical layout components from 32 nm to 28 and 22 nm with respect to process variability metrics. Starting from the description of a mature LPV flow, the paper illustrates the core methodology for deriving a metric for design scalability. The functional dependency between the scalability metric and the scaling factor can then be modeled to study the scaling robustness of a set of representative layouts. Conversely, quantitative data on scalability limits can be used to determine which design rules can be pushed and which must be relaxed in the transition from 32 to 22 nm.

Paper Details

Date Published: 12 March 2009
PDF: 10 pages
Proc. SPIE 7275, Design for Manufacturability through Design-Process Integration III, 727511 (12 March 2009); doi: 10.1117/12.814253
Show Author Affiliations
Jason P. Cain, Advanced Micro Devices (United States)
Luigi Capodieci, Advanced Micro Devices (United States)


Published in SPIE Proceedings Vol. 7275:
Design for Manufacturability through Design-Process Integration III
Vivek K. Singh; Michael L. Rieger, Editor(s)

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