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Proceedings Paper

EUV lithography for 30nm half pitch and beyond: exploring resolution, sensitivity, and LWR tradeoffs
Author(s): E. Steve Putna; Todd R. Younkin; Manish Chandhok; Kent Frasure
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Paper Abstract

The International Technology Roadmap for Semiconductors (ITRS) denotes Extreme Ultraviolet (EUV) lithography as a leading technology option for realizing the 32nm half-pitch node and beyond. Readiness of EUV materials is currently one high risk area according to assessments made at the 2008 EUVL Symposium. The main development issue regarding EUV resist has been how to simultaneously achieve high sensitivity, high resolution, and low line width roughness (LWR). This paper describes the strategy and current status of EUV resist development at Intel Corporation. Data is presented utilizing Intel's Micro-Exposure Tool (MET) examining the feasibility of establishing a resist process that simultaneously exhibits ≤30nm half-pitch (HP) L/S resolution at ≤10mJ/cm2 with ≤4nm LWR.

Paper Details

Date Published: 1 April 2009
PDF: 9 pages
Proc. SPIE 7273, Advances in Resist Materials and Processing Technology XXVI, 72731L (1 April 2009); doi: 10.1117/12.814191
Show Author Affiliations
E. Steve Putna, Intel Corp. (United States)
Todd R. Younkin, Intel Corp. (United States)
Manish Chandhok, Intel Corp. (United States)
Kent Frasure, Intel Corp. (United States)


Published in SPIE Proceedings Vol. 7273:
Advances in Resist Materials and Processing Technology XXVI
Clifford L. Henderson, Editor(s)

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