Share Email Print
cover

Proceedings Paper

Self-aligned double-gate (DG) nanoscale vertical MOSFETs with reduced parasitic capacitance
Author(s): Razali Ismail; Ismail Saad
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

Enhanced symmetrical self-aligned double-gate (DG) vertical nMOSFET with low parasitic capacitance is presented. The process utilizes the oblique rotating ion implantation (ORI) method combined with fillet local oxidation (FILOX) technology (FILOX + ORI). Self-aligned region forms a sharp vertical channel profile that increased the number of electrons in the channel. These have improved drive-on current and drain-induced-barrier-lowering (DIBL) effect with a reduced off-state leakage current tremendously. The gate-to-drain capacitance is significantly reduced while having a small difference of gate-to-source capacitance compared to FILOX device. The drain overlap capacitance is a factor of 0.2 lower and the source overlap capacitance is a factor of 1.5 lower than standard vertical MOSFETs.

Paper Details

Date Published: 30 December 2008
PDF: 9 pages
Proc. SPIE 7268, Smart Structures, Devices, and Systems IV, 72680U (30 December 2008); doi: 10.1117/12.814129
Show Author Affiliations
Razali Ismail, Univ. Teknologi Malaysia (Malaysia)
Ismail Saad, Univ. Malaysia Sabah (Malaysia)


Published in SPIE Proceedings Vol. 7268:
Smart Structures, Devices, and Systems IV
Said Fares Al-Sarawi; Vijay K. Varadan; Neil Weste; Kourosh Kalantar-Zadeh, Editor(s)

© SPIE. Terms of Use
Back to Top