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Proceedings Paper

Important challenges for line-width-roughness reduction
Author(s): Hidetami Yaegashi; M. Kushibiki; E. Nishimura; S. Shimura; F. Iwao; T. Kawasaki; K. Hasebe; H. Murakami; A. Hara; K. Yabe
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Paper Abstract

It is supposed that double patterning process is one of the promising candidates for making mask pattern for dry etching at 32nm and 22nm node. Currently, drastic improvement of overlay of scanner is considered to be the most important challenge and much attention has been paid to sidewall spacer process since it can avoid that problem and also can provide easier method to fabricate patterns repeatedly. In this paper, material option of core pattern, spacer pattern and hard mask, which are main components of this process, is presented and 32nm gate pattern is actually fabricated after process optimization. In addition, line-width-roughness (LWR), whose reduction is becoming more and more necessary, is measured in each process step of spacer process.

Paper Details

Date Published: 1 April 2009
PDF: 6 pages
Proc. SPIE 7273, Advances in Resist Materials and Processing Technology XXVI, 72732H (1 April 2009); doi: 10.1117/12.814126
Show Author Affiliations
Hidetami Yaegashi, Tokyo Electron Ltd. (Japan)
M. Kushibiki, Tokyo Electron AT Ltd. (Japan)
E. Nishimura, Tokyo Electron AT Ltd. (Japan)
S. Shimura, Tokyo Electron Kyushu Ltd. (Japan)
F. Iwao, Tokyo Electron Kyushu Ltd. (Japan)
T. Kawasaki, Tokyo Electron Kyushu Ltd. (Japan)
K. Hasebe, Tokyo Electron Tohoku Ltd. (Japan)
H. Murakami, Tokyo Electron Tohoku Ltd. (Japan)
A. Hara, Tokyo Electron Ltd. (Japan)
K. Yabe, Tokyo Electron Ltd. (Japan)

Published in SPIE Proceedings Vol. 7273:
Advances in Resist Materials and Processing Technology XXVI
Clifford L. Henderson, Editor(s)

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