Share Email Print
cover

Proceedings Paper

The PIXBAR OPC for contact-hole pattern in sub-70-nm generation
Author(s): KunYuan Chen; ChunCheng Liao; ShuHao Chen; Todd Wey; Phoeby Cheng; Pinjan Chou; Jochen Schacht; Dyiann Chou; Srividya Jayaram
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

As semiconductor technologies move toward 70nm generation and below, contact-hole is one of the most challenging features to print on wafer. There are two principle difficulties in defining small contact-hole patterns on wafer. One is insufficient process margin besides poor resolution compared with line-space pattern. The other is that contact-hole should be made through pitches and random contact-hole pattern should be fabricated from time to time. PIXBAR technology is the candidate which can help improve the process margin for random contact-holes. The PIXBAR technology lithography attempts to synthesize the input mask which leads to the desired output wafer pattern by inverting the forward model from mask to wafer. This paper will use the pixel-based mask representation, a continuous function formulation, and gradient-based interactive optimization techniques to solve the problem. The result of PIXBAR method helps gain improvement in process window with a short learning cycle in contact-hole pattern assist-feature testing.

Paper Details

Date Published: 13 March 2009
PDF: 6 pages
Proc. SPIE 7275, Design for Manufacturability through Design-Process Integration III, 72750Z (13 March 2009); doi: 10.1117/12.813985
Show Author Affiliations
KunYuan Chen, Nanya Technology Corp. (Taiwan)
ChunCheng Liao, Nanya Technology Corp. (Taiwan)
ShuHao Chen, Nanya Technology Corp. (Taiwan)
Todd Wey, Nanya Technology Corp. (Taiwan)
Phoeby Cheng, Nanya Technology Corp. (Taiwan)
Pinjan Chou, Mentor Graphics Taiwan (Taiwan)
Jochen Schacht, Mentor Graphics Taiwan (Taiwan)
Dyiann Chou, Mentor Graphics Corp. (United States)
Srividya Jayaram, Mentor Graphics Corp. (United States)


Published in SPIE Proceedings Vol. 7275:
Design for Manufacturability through Design-Process Integration III
Vivek K. Singh; Michael L. Rieger, Editor(s)

© SPIE. Terms of Use
Back to Top