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Proceedings Paper

Layout electrical cooptimization for increased tolerance to process variations
Author(s): Lionel Riviere-Cazaux; Philippe Hurat; Bala Kasthuri; Larry Layton; Nishath Verghese
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Paper Abstract

To address the variability challenges inherent to 45 and 32nm as early as possible, a model-based variability analysis has been implemented to predict lithography induced electrical variability in standard cell libraries, and this analysis was used optimize the cell layout and decrease variability by up to 40%.

Paper Details

Date Published: 13 March 2009
PDF: 7 pages
Proc. SPIE 7275, Design for Manufacturability through Design-Process Integration III, 727506 (13 March 2009); doi: 10.1117/12.813969
Show Author Affiliations
Lionel Riviere-Cazaux, Freescale Semiconductor, Inc. (United States)
Philippe Hurat, Cadence Design Systems, Inc. (United States)
Bala Kasthuri, Cadence Design Systems, Inc. (United States)
Larry Layton, Cadence Design Systems, Inc. (United States)
Nishath Verghese, Cadence Design Systems, Inc. (United States)


Published in SPIE Proceedings Vol. 7275:
Design for Manufacturability through Design-Process Integration III
Vivek K. Singh; Michael L. Rieger, Editor(s)

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