Share Email Print

Proceedings Paper

High-performance bridge-style full adder structure
Author(s): Omid Kavehei; Said F. Al-Sarawi; Derek Abbott; Keivan Navi
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

Adders are the core element in arithmetic circuits like subtracters, multipliers, and dividers. Optimization of adders can be achieved at device, circuit, architectural, and algorithmic levels. In this paper we present a new optimize full adder circuit structure that provides an improved performance compared to standard and mirror types adder structures. The performance of this adder in terms of power, delay, energy, and yield are investigated. This paper also proposes a novel simulation setup for full adder cells that is suitable for analyzing full adder cells at the high frequency. The simulation results of this structure will take into account the process variations for a 90 nm CMOS process and present results based on post-layout simulation using Cadence and Synopsys tools.

Paper Details

Date Published: 30 December 2008
PDF: 9 pages
Proc. SPIE 7268, Smart Structures, Devices, and Systems IV, 72680D (30 December 2008); doi: 10.1117/12.813924
Show Author Affiliations
Omid Kavehei, The Univ. of Adelaide (Australia)
Said F. Al-Sarawi, The Univ. of Adelaide (Australia)
Derek Abbott, The Univ. of Adelaide (Australia)
Keivan Navi, Shahid Beheshti Univ. (Iran, Islamic Republic of)

Published in SPIE Proceedings Vol. 7268:
Smart Structures, Devices, and Systems IV
Said Fares Al-Sarawi; Vijay K. Varadan; Neil Weste; Kourosh Kalantar-Zadeh, Editor(s)

© SPIE. Terms of Use
Back to Top