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Proceedings Paper

Study of devices leakage of 45nm node with different SRAM layouts using an advanced e-beam inspection systems
Author(s): Hong Xiao; Long Ma; Yan Zhao; Jack Jau
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Paper Abstract

In this study, a nickel silicide (NiSi) wafer and a WCMP wafer were used. We captured bright voltage contract (BVC) defects at N+/P-well on NiSi wafer, we also captured N+/P-well leak/short defects on WCMP wafer as BVC defects in positive mode inspection and dark voltage contrast (DVC) defects in Negative ModeTM inspection. N+/P-well leakage signatures of the two inspection modes of WCMP strongly correlate with each other, which indicate they are the same defects. N+/P-well leakage signature on WCMP wafer also correlate with that on NiSi wafer. With negative mode inspection, we captured P+/N-well leakage on WCMP wafer at two different static random access memory (SRAM) arrays (SRAM1 and SRAM3) as DVC defects. The P+/N-well leakage signature is very different from N+/P-well leakage signature in SRAM3. P+/N-well leakage signature of SRAM1 is also very different from that of SRAM3. This study confirmed our prediction that different SRAM layout will cause different P+/N-well leakage, especially in the case of over etching of share contact hole.

Paper Details

Date Published: 23 March 2009
PDF: 10 pages
Proc. SPIE 7272, Metrology, Inspection, and Process Control for Microlithography XXIII, 72721E (23 March 2009); doi: 10.1117/12.813885
Show Author Affiliations
Hong Xiao, Hermes Microvision, Inc. (United States)
Long Ma, Hermes Microvision, Inc. (United States)
Yan Zhao, Hermes Microvision, Inc. (United States)
Jack Jau, Hermes Microvision, Inc. (United States)


Published in SPIE Proceedings Vol. 7272:
Metrology, Inspection, and Process Control for Microlithography XXIII
John A. Allgair; Christopher J. Raymond, Editor(s)

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