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Proceedings Paper

Design specific variation in pattern transfer by via/contact etch process: full-chip analysis
Author(s): Valeriy Sukharev; Ara Markosian; Armen Kteyan; Levon Manukyan; Nikolay Khachatryan; Jun-Ho Choy; Hasmik Lazaryan; Henrik Hovsepyan; Seiji Onoue; Takuo Kikuchi; Tetsuya Kamigaki
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Paper Abstract

A novel model-based algorithm provides a capability to control full-chip design specific variation in pattern transfer caused by via/contact etch processes. This physics based algorithm is capable of detecting and reporting etch hotspots based on the fab defined thresholds of acceptable variations in critical dimension (CD) of etched shapes. It can be used also as a tool for etch process optimization to capture the impact of a variety of patterns presented in a particular design. A realistic set of process parameters employed by the developed model allows using this novel via-contact etch (VCE) EDA tool for the design aware process optimization in addition to the "standard" process aware design optimization.

Paper Details

Date Published: 13 March 2009
PDF: 12 pages
Proc. SPIE 7275, Design for Manufacturability through Design-Process Integration III, 72750H (13 March 2009); doi: 10.1117/12.813882
Show Author Affiliations
Valeriy Sukharev, Mentor Graphics Corp. (United States)
Ara Markosian, Mentor Graphics Corp. (United States)
Armen Kteyan, Mentor Graphics Corp. (United States)
Levon Manukyan, Mentor Graphics Corp. (United States)
Nikolay Khachatryan, Mentor Graphics Corp. (United States)
Jun-Ho Choy, Mentor Graphics Corp. (United States)
Hasmik Lazaryan, Mentor Graphics Corp. (United States)
Henrik Hovsepyan, Mentor Graphics Corp. (United States)
Seiji Onoue, Toshiba Corp. (Japan)
Takuo Kikuchi, Toshiba Corp. (Japan)
Tetsuya Kamigaki, Toshiba Corp. Semiconductor Co. (Japan)


Published in SPIE Proceedings Vol. 7275:
Design for Manufacturability through Design-Process Integration III
Vivek K. Singh; Michael L. Rieger, Editor(s)

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