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Proceedings Paper

Computational requirements for OPC
Author(s): Chris Spence; Scott Goad
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Paper Abstract

In this paper, we provide some data on the actual scaling of OPC runtime that we have experienced at AMD. We review the expected OPC requirements down to the 16 nm node and develop a model to predict the total CPU requirements to process a single chip design. We will also review the scalability of "hardware acceleration" under a variety of scenarios.

Paper Details

Date Published: 12 March 2009
PDF: 9 pages
Proc. SPIE 7275, Design for Manufacturability through Design-Process Integration III, 72750U (12 March 2009); doi: 10.1117/12.813522
Show Author Affiliations
Chris Spence, Advanced Micro Devices, Inc. (United States)
Scott Goad, Advanced Micro Devices, Inc. (United States)


Published in SPIE Proceedings Vol. 7275:
Design for Manufacturability through Design-Process Integration III
Vivek K. Singh; Michael L. Rieger, Editor(s)

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