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Proceedings Paper

Resist process control for 32-nm logic node and beyond with NA > 1.30 immersion exposure tool
Author(s): Seiji Nagahara; Kazuhiro Takahata; Seiji Nakagawa; Takashi Murakami; Kazuhiro Takeda; Shinpei Nakamura; Makoto Ueki; Masaki Satake; Tatsuhiko Ema; Hiroharu Fujise; Hiroki Yonemitsu; Yuriko Seino; Shinichiro Nakagawa; Masafumi Asano; Yosuke Kitamura; Takayuki Uchiyama; Shoji Mimotogi; Makoto Tominaga
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Paper Abstract

Resist process challenges for 32-nm node and beyond are discussed in this paper. For line and space (L/S) logic patterns, we examine ways to balance the requirements of resolution-enhancement techniques (RETs). In 32-nm node logic patterning, two-dimensional (2D) layout pattern deformation becomes more severe with stronger RET (e.g., narrow angle CQUAD illumination). Also pattern collapse more frequently happens in 2D-pattern layouts when stronger RET is used. In contrast, milder RET (annular illumination) does not induce the severe pattern collapse in 2D-pattern layout. For 2D-pattern layouts, stronger RET seems to worsen image contrast and results in high background-light in the resist pattern, which induces more pattern collapse. For the minimum-pitch L/S pattern in 32-nm node logic, annular illumination is acceptable for patterning with NA1.35 scanner when high contrast resist is used. For contact/via patterns, it is necessary to expand the overlapping CD process window. Better process margin is realized through the combination of hole-shrink technique and precise acid-diffusion control in an ArF chemically amplified resist.

Paper Details

Date Published: 1 April 2009
PDF: 11 pages
Proc. SPIE 7273, Advances in Resist Materials and Processing Technology XXVI, 72733A (1 April 2009); doi: 10.1117/12.813498
Show Author Affiliations
Seiji Nagahara, NEC Electronics Corp. (Japan)
Kazuhiro Takahata, Toshiba Corp. (Japan)
Seiji Nakagawa, Toshiba Corp. (Japan)
Takashi Murakami, NEC Electronics Corp. (Japan)
Kazuhiro Takeda, NEC Electronics Corp. (Japan)
Shinpei Nakamura, NEC Electronics Corp. (Japan)
Makoto Ueki, NEC Electronics Corp. (Japan)
Masaki Satake, Toshiba Corp. (Japan)
Tatsuhiko Ema, Toshiba Corp. (Japan)
Hiroharu Fujise, Toshiba Corp. (Japan)
Hiroki Yonemitsu, Toshiba Corp. (Japan)
Yuriko Seino, Toshiba Corp. (Japan)
Shinichiro Nakagawa, Toshiba Corp. (Japan)
Masafumi Asano, Toshiba Corp. (Japan)
Yosuke Kitamura, Toshiba Corp. (Japan)
Takayuki Uchiyama, NEC Electronics Corp. (Japan)
Shoji Mimotogi, Toshiba Corp. (Japan)
Makoto Tominaga, NEC Electronics Corp. (Japan)

Published in SPIE Proceedings Vol. 7273:
Advances in Resist Materials and Processing Technology XXVI
Clifford L. Henderson, Editor(s)

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