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Proceedings Paper

Fabrication of half-pitch 32-45-nm SRAM patterns with EUVL
Author(s): Yuusuke Tanaka; Hajime Aoyama; Shunko Magoshi; Kazuo Tawarayama; Seiichiro Shirai; Hiroyuki Tanaka
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Paper Abstract

Since the k1 factor is much larger in extreme-ultraviolet lithography (EUVL) than in optical lithography, optical proximity correction (OPC) should be much simpler for patterns on EUVL masks than for those on advanced photomasks. This will facilitate the fabrication of complex device patterns with EUVL. In this study, static random-access memory (SRAM) cell patterns for the half-pitch (hp) 32- and 45-nm nodes were fabricated using two EUV exposure tools (SFET, EUV1), and their fidelity was evaluated. The levels of SRAM patterns were isolation, gate, contact, and metal. The size of the SRAM unit cell was 0.191 μm2 for the hp 45-nm and 0.097 μm2 for the hp 32-nm patterns. Most of the experiments employed SSR2, a high-resolution EUV resist. The high performance of the SFET and SSR2 enabled hp 45-nm SRAM patterns to be fabricated faithfully. However, some of the hp 32-nm patterns deviated from the mask patterns. To determine the causes of this degradation, we made a simulation analysis using the Sentaurus Lithography simulator. The main cause of the degradation was found to be resist blur. When we used MET-2D resist, which has a relatively large resist blur, the degradation became quite severe. Although the resist blur for SSR2 is about 10 nm, it is not small enough for the hp 32-nm SRAM patterns, especially for the gate and metal levels. It is necessary to reduce resist blur to improve the fidelity for this pattern size. Simulation results indicated that resist blur should be reduced to about 5 nm for hp 22-nm node device patterns.

Paper Details

Date Published: 18 March 2009
PDF: 12 pages
Proc. SPIE 7271, Alternative Lithographic Technologies, 72713S (18 March 2009); doi: 10.1117/12.813492
Show Author Affiliations
Yuusuke Tanaka, Semiconductor Leading Edge Technologies, Inc. (Japan)
Hajime Aoyama, Semiconductor Leading Edge Technologies, Inc. (Japan)
Shunko Magoshi, Semiconductor Leading Edge Technologies, Inc. (Japan)
Kazuo Tawarayama, Semiconductor Leading Edge Technologies, Inc. (Japan)
Seiichiro Shirai, Semiconductor Leading Edge Technologies, Inc. (Japan)
Hiroyuki Tanaka, Semiconductor Leading Edge Technologies, Inc. (Japan)

Published in SPIE Proceedings Vol. 7271:
Alternative Lithographic Technologies
Frank M. Schellenberg; Bruno M. La Fontaine, Editor(s)

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