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Proceedings Paper

Process liability evaluation for EUVL
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Paper Abstract

This paper concerns the readiness of extreme ultraviolet lithography (EUVL) for high-volume manufacture based on accelerated development in critical areas and the construction of a process liability (PL) test site that integrates results in these areas. The overall lithography performance was determined from the performance of the exposure tool, the printability obtainable with the resist, mask fabrication with accurate critical dimension (CD) control, and correction technology for mask data preparation. The EUV1 exposure tool can carry out exposure over the full field (26 mm × 33 mm) at a resolution high enough for 32-nm line-and-space patterns when Selete Standard Resist 3 (SSR3) is used. Thus, the test site was designed for the full-field exposure of various pattern sizes [half-pitch (hp) 32-50 nm]. The CD variation of the mask was found to be as good as 2.8 nm (3σ); and only one printable defect was detected. The effect of flare on CD variation is a critical issue in EUVL; so flare was compensated for based on the point spread function for the projection optics of the EUV1 and aerial simulations that took resist blur into account. The accuracy obtained when an electronic design automation (EDA) tool was used for mask resizing was found to be very good (error ≤ ±2 nm). Metal wiring patterns with a size of hp 32 nm were successfully formed by wafer processing. The production readiness of EUVL based on the integration of results in these areas was evaluated by electrical tests on low-resistance tungsten wiring. The yield for the electrically open test for hp 50 nm (32-nm logic node) and hp 40 nm (22-nm logic node) were found to be over 60% and around 50%, respectively; and the yield tended to decrease as patterns became smaller. We found the PL test site to be very useful for determining where further improvements need to be made and for evaluating the production readiness of EUVL.

Paper Details

Date Published: 17 March 2009
PDF: 12 pages
Proc. SPIE 7271, Alternative Lithographic Technologies, 727120 (17 March 2009); doi: 10.1117/12.813484
Show Author Affiliations
Hajime Aoyama, Semiconductor Leading Edge Technologies, Inc. (Japan)
Kazuo Tawarayama, Semiconductor Leading Edge Technologies, Inc. (Japan)
Yuusuke Tanaka, Semiconductor Leading Edge Technologies, Inc. (Japan)
Daisuke Kawamura, Semiconductor Leading Edge Technologies, Inc. (Japan)
Yukiyasu Arisawa, Semiconductor Leading Edge Technologies, Inc. (Japan)
Taiga Uno, Semiconductor Leading Edge Technologies, Inc. (Japan)
Takashi Kamo, Semiconductor Leading Edge Technologies, Inc. (Japan)
Toshihiko Tanaka, Semiconductor Leading Edge Technologies, Inc. (Japan)
Toshiro Itani, Semiconductor Leading Edge Technologies, Inc. (Japan)
Hiroyuki Tanaka, Semiconductor Leading Edge Technologies, Inc. (Japan)
Yumi Nakajima, Toshiba Corp. Semiconductor Co. (Japan)
Ryoichi Inanami, Toshiba Corp. Semiconductor Co. (Japan)
Kosuke Takai, Toshiba Corp. Semiconductor Co. (Japan)
Koji Murano, Toshiba Corp. Semiconductor Co. (Japan)
Takeshi Koshiba, Toshiba Corp. Semiconductor Co. (Japan)
Kohji Hashimoto, Toshiba Corp. Semiconductor Co. (Japan)
Ichiro Mori, Semiconductor Leading Edge Technologies, Inc. (Japan)


Published in SPIE Proceedings Vol. 7271:
Alternative Lithographic Technologies
Frank M. Schellenberg; Bruno M. La Fontaine, Editor(s)

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