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Proceedings Paper

Experimental evaluation of particulate contamination on backside of EUV reticle
Author(s): Kazuya Ota; Takao Taguchi; Mitsuaki Amemiya; Naosuke Nishimura; Osamu Suga
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Paper Abstract

"Reticle protection during storage, handling and use" is one of the critical issues of EUV lithography because no practical pellicle has been found for EUV reticles as yet. The front surface of an EUV reticle has to be protected from particles larger than 20-30 nm to maintain the image quality projected on the wafer plane, and the backside also has to be protected to maintain the flatness of the reticle chucked on an electrostatic chuck (ESC). In this paper, we are focusing on particles on the backside of a reticle. If a particle lies between a reticle and a chuck, it has a strong impact on the flatness of the reticle, and the wafer overlay is degraded by out-of-plane distortion (OPD) and in-plane distortion (IPD) caused by the particle. From this point of view, we need to know the maximum allowable size of particles on the backside of a reticle. MIRAI-Selete introduced an experimental setup that can measure the flatness of the chucked reticle in a vacuum. Two electrostatic chucks were alternately installed in the vacuum chamber of Mask Protection Engineering Tool (MPE Tool), a reticle is automatically carried from a reticle pod to the chuck in the tool. The flatness of the reticle can be measured by an interferometer through the viewport underneath the chamber. We report results of experimental evaluation about the relationship between the reticle OPD and the initial size of particles and mention the maximum allowable size of particles between a reticle and a chuck.

Paper Details

Date Published: 18 March 2009
PDF: 8 pages
Proc. SPIE 7271, Alternative Lithographic Technologies, 72713M (18 March 2009); doi: 10.1117/12.812952
Show Author Affiliations
Kazuya Ota, Semiconductor Leading Edge Technologies, Inc. (Japan)
Takao Taguchi, Semiconductor Leading Edge Technologies, Inc. (Japan)
Mitsuaki Amemiya, Semiconductor Leading Edge Technologies, Inc. (Japan)
Naosuke Nishimura, Semiconductor Leading Edge Technologies, Inc. (Japan)
Osamu Suga, Semiconductor Leading Edge Technologies, Inc. (Japan)


Published in SPIE Proceedings Vol. 7271:
Alternative Lithographic Technologies
Frank M. Schellenberg; Bruno M. La Fontaine, Editor(s)

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