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Proceedings Paper

Application results of lot-to-lot high-order overlay correction for sub-60-nm memory device fabrication
Author(s): Jangho Shin; Sangmo Nam; Taekyu Kim; Yong-Kug Bae; Junghyeon Lee
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Paper Abstract

According to the international technology roadmap for semiconductors 2007 overlay error should be controlled under 12 nm for sub-60-nm memory devices. To meet such a tight requirement, lot-to-lot high order overlay correction (HOC) is evaluated for the gate and contact layers of dynamic random access memory. A commercial package of HOC is available from scanner makers such as ASML, Canon, and Nikon. Note that only wafer corrections are investigated for this particular experiment. Reticle corrections are excluded. Experimental results verify 1 to 3 nm of overlay improvement by applying HOC. However, the amount of improvement is layer (process) dependent. It turned out that HOC is not an overall solution. It should be applied carefully for a certain process conditions. Detailed experimental results are discussed.

Paper Details

Date Published: 23 March 2009
PDF: 5 pages
Proc. SPIE 7272, Metrology, Inspection, and Process Control for Microlithography XXIII, 72721R (23 March 2009); doi: 10.1117/12.812193
Show Author Affiliations
Jangho Shin, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Sangmo Nam, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Taekyu Kim, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Yong-Kug Bae, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Junghyeon Lee, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)


Published in SPIE Proceedings Vol. 7272:
Metrology, Inspection, and Process Control for Microlithography XXIII
John A. Allgair; Christopher J. Raymond, Editor(s)

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