Share Email Print
cover

Proceedings Paper

An efficient scan diagnosis methodology according to scan failure mode for yield enhancement
Author(s): Jung-Tae Kim; Nam-Sik Seo; Ghil-Geun Oh; Dae-Gue Kim; Kyu-Taek Lee; Chi-Young Choi; InSoo Kim; Hyoung Bok Min
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

Yield has always been a driving consideration during fabrication of modern semiconductor industry. Statistically, the largest portion of wafer yield loss is defective scan failure. This paper presents efficient failure analysis methods for initial yield ramp up and ongoing product with scan diagnosis. Result of our analysis shows that more than 60% of the scan failure dies fall into the category of shift mode in the very deep submicron (VDSM) devices. However, localization of scan shift mode failure is very difficult in comparison to capture mode failure because it is caused by the malfunction of scan chain. Addressing the biggest challenge, we propose the most suitable analysis method according to scan failure mode (capture / shift) for yield enhancement. In the event of capture failure mode, this paper describes the method that integrates scan diagnosis flow and backside probing technology to obtain more accurate candidates. We also describe several unique techniques, such as bulk back-grinding solution, efficient backside probing and signal analysis method. Lastly, we introduce blocked chain analysis algorithm for efficient analysis of shift failure mode. In this paper, we contribute to enhancement of the yield as a result of the combination of two methods. We confirm the failure candidates with physical failure analysis (PFA) method. The direct feedback of the defective visualization is useful to mass-produce devices in a shorter time. The experimental data on mass products show that our method produces average reduction by 13.7% in defective SCAN & SRAM-BIST failure rates and by 18.2% in wafer yield rates.

Paper Details

Date Published: 30 December 2008
PDF: 9 pages
Proc. SPIE 7268, Smart Structures, Devices, and Systems IV, 72681H (30 December 2008); doi: 10.1117/12.812091
Show Author Affiliations
Jung-Tae Kim, Samsung Electronics (Korea, Republic of)
Sungkyunkwan Univ. (Korea, Republic of)
Nam-Sik Seo, Samsung Electronics (Korea, Republic of)
Ghil-Geun Oh, Samsung Electronics (Korea, Republic of)
Dae-Gue Kim, Samsung Electronics (Korea, Republic of)
Kyu-Taek Lee, Samsung Electronics (Korea, Republic of)
Chi-Young Choi, Samsung Electronics (Korea, Republic of)
InSoo Kim, Sungkyunkwan Univ. (Korea, Republic of)
Hyoung Bok Min, Sungkyunkwan Univ. (Korea, Republic of)


Published in SPIE Proceedings Vol. 7268:
Smart Structures, Devices, and Systems IV
Said Fares Al-Sarawi; Vijay K. Varadan; Neil Weste; Kourosh Kalantar-Zadeh, Editor(s)

© SPIE. Terms of Use
Back to Top